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mirror of https://github.com/xtacocorex/CHIP_IO synced 2025-07-20 12:53:22 +00:00
Commit Graph

82 Commits

Author SHA1 Message Date
a4dd1558f0 Realized that the AP-EINT1/3 test code wasn't actually testing callbacks, they do work properly in my testing. Reverting gptest.py to what it was. Revision Update. Issue #9 is resolved. 2016-07-10 19:23:45 -05:00
3d1ecb6b5e Edge detection callback is now working for the XIO's. Blocking wait_for_edge works for both the AP-EINT1/3 and the XIO's. Need to figure out why AP-EINT1/3 don't work for the callback. This is to help fix issue #9. 2016-07-10 16:37:22 -05:00
db4493322d Inital attempt at fixing #9. Things are still broken. wait_for_edge no longer works on AP-EINT1/3, XIO will trigger only one on falling edge. 2016-07-10 14:56:40 -05:00
a9a2dbf862 Updating the version prior to merge of this branch into master 2016-07-09 22:26:50 -05:00
7812063991 Fixed softpwm bug ("disable" code didn't synchronize thread exit) 2016-07-09 18:42:38 -05:00
0c6579914c Implementing alternate names per issue #7, still need to pull the pin names/alt-names/keys into the readme 2016-07-05 20:50:49 -05:00
45ba0e5332 More error checking work 2016-07-04 14:45:41 -05:00
694aa37f23 Testing and error handling 2016-07-04 14:35:45 -05:00
0e7d03c472 Fixed a bunch of error handling 2016-07-04 13:56:11 -05:00
9ee83c0b38 Adding Python interface to get the base XIO numbers, fixes for gptest.py on the 4.4 kernel CHIPs 2016-07-03 11:49:17 -05:00
71b6829804 Reworked a lot of error handling. 2016-07-02 18:57:03 -05:00
093922567a Added a bunch of sanity checking 2016-06-26 14:28:06 -05:00
1f4714a351 Got rid of last of GPIO port constants from code. 2016-06-25 20:02:45 -05:00
34167a9574 Some (not all) of the changes for the new XIO base addr 2016-06-21 17:40:00 -05:00
0f89ae462c Simple updated to the XIO base logic based upon suggestions by fordsford 2016-06-18 15:06:39 -05:00
99193144f1 Stupid logic error preventing XIO-P1 or higher to work. Fixed now 2016-06-18 14:44:36 -05:00
818be5202e Fixing the code to handle pulling the right XIO base number due to the change in the CHIP OS 1.1 with the 4.4 kernel, thanks to howientc and fordsfords for their help 2016-06-18 14:34:41 -05:00
2ebbffd137 Edits copyright name on SOFTPWM files 2016-05-09 18:42:36 +00:00
3c912ecb72 Reverts accidental change to c_pwm 2016-05-06 17:38:51 +00:00
f5063c199c Corrects backwards polarity 2016-05-06 17:30:14 +00:00
9ef55ede59 Makes default polarity 1 2016-05-06 17:30:13 +00:00
2f3172568a Fixes bugs with creating thread. Forces 0 and 100 duty cycles 2016-05-06 17:30:13 +00:00
41203a46a6 Adds mutex protection 2016-05-06 17:30:12 +00:00
d7bf982b11 Adds softpwm disabling and restructures thread 2016-05-06 17:30:12 +00:00
9645d2aae3 Sets up softpwm struct and thread 2016-05-06 17:30:11 +00:00
9ac22c32cd Adds softpwm files 2016-05-06 17:30:11 +00:00
777fda06a3 Fixing issue #2, edge detection for the XIO pins now works, simple logic issue in the if statement for throwing errors if gpio number is bad 2016-04-18 19:31:08 -05:00
0e1cf46c4e Addressing Issue #1, adding the ability to set the AP-EINT1 and AP-EINT3 pins as useable for edge detection and callbacks 2016-04-08 21:47:42 -05:00
c2ab013a5d Adding protection for to the GPIO to only allow edge detection and call back on the XIO pins, clean up of the PWM, updated test code 2016-04-02 19:48:57 -05:00
cea44c287d PWM support fixed, the test fails when trying to change the frequency, but I don't think that's an issue. Have not run this against something that needs PWM to operate, but the .dtb I have loaded has /sys/class/pwm/pwmchip0 and it can be configured with this code 2016-02-29 13:04:35 -06:00
9d593828ae Initial PWM support for the CHIP even though the base .dtb does not support, this is untested 2016-02-25 22:38:58 -06:00
01ae605491 Initial commit, working GPIO for all available CHIP GPIO pins, have not tested edge detection and callbacks 2016-02-24 21:48:40 -06:00